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ECE Departmental Seminar

Hardware Acceleration for Deep Learning

Prof. Peter Milder

Peter MilderFriday, 2/17/17, 11:00am
Light Engineering 250

Abstract: Deep learning and convolutional neural networks (CNNs) are revolutionizing machine learning applications such as computer vision, fraud detection, and natural language processing. At tasks such as visual object detection and classification, deep CNN-based systems are consistently improving on the state of the art. However, these algorithmic breakthroughs have come at a steep computational cost, necessitating the use of new hardware to enable this rapid growth to continue. This talk will describe recent progress on using field programmable gate arrays (FPGAs) to accelerate deep learning algorithms, focusing on new structures that exhibit better utilization of FPGA resources, and on new algorithms that greatly reduce the off-chip data bandwidth required by the accelerator.

Bio: Peter Milder is an Assistant Professor in the Department of Electrical and Computer Engineering at Stony Brook University. His research focuses on FPGA hardware acceleration, exploring how we can use computer-based tools and systems to make FPGA acceleration more efficient and easier to use. Peter received the BS, MS, and PhD degrees in Electrical and Computer Engineering from Carnegie Mellon University in 2004, 2005, and 2010, respectively. From 2010–2012, he was a post-doctoral researcher at Carnegie Mellon, and in 2012 he joined the faculty of Stony Brook. In 2014 he was the winner of the Best Paper Award from ACM Transactions on Design Automation of Electronic Systems.