Leveraging Monolithic 3D Integrated Circuit Technology for Emerging Applications
December 14, 2018
Light Engineering room 250
Advisor: Prof. Emre Salman
Three-dimensional (3D) integrated circuits have emerged as an effective solution to some of the critical issues encountered in planar technologies such as longer global interconnects and difficulty in scaling the transistors. More recently, interest on monolithic 3D integration has grown due to encouraging developments on sequentially fabricating multiple transistor layers on a single substrate.
In this dissertation, an open source cell library and a fully functional process design kit (PDK) are developed for both transistor-level and gate-level monolithic 3D integration technology. The proposed cell library is used to evaluate the power and timing characteristics of multiple benchmark circuits and a 128-point FFT core with approximately 330K cells. The effect of routing congestion on timing characteristics is stronger in monolithic 3D technology due to significant reduction in footprint. Three versions of the cell library with different heights are developed to investigate effect of number of routing tracks on area, power, and delay characteristics. Clock characteristics of the FFT core are also investigated.
The security of integrated circuits has emerged as a fundamental issue due to the threats from the globalized semiconductor supply chain. Monolithic 3D integrated circuits introduce novel opportunities and challenges on managing hardware security. The PDK and cell library are used to develop an efficient logic camouflaging method for monolithic 3D integrated circuits. Logic camouflaging is a layout-level technique to thwart image analysis based reverse engineering attacks. Full custom cell libraries are developed and characterized to camouflage large scale 2D and 3D circuits. The methodology is implemented and evaluated using a SIMON block cipher and several ISCAS'89 benchmark circuits.
The thermal management of monolithic 3D integrated circuits is more challenging than 2D circuits due to the reduced circuit area (hence, greater power density) and the low thermal conductivity of the inter-layer dielectric material. The thermal integrity of monolithic 3D circuits is explored at the physical level. A design flow is developed to obtain both steady state and transient temperature profiles of monolithic 3D integrated circuits. The entire proposed PDK, libraries and related files for tool integration are publicly available to facilitate future research.