Electron tunneling has long been used as a tool to investigate the properties of thin-film materials. It is also the underlying phenomenon of a large range of electronic devices, including applications in the semiconductor industry, particularly, nonvolatile memory cells. This project investigates metal-insulator-metal (MIM) structures with aluminum oxide as the dielectric layer. The purpose of this investigation is to determine the parameters that are characteristic of aluminum oxide grown as dielectric thin-films in view of the development of the fabrication technology necessary to process crested tunnel barriers.
The crested tunnel barriers would have a trilayered structure with the middle layer having the highest barrier height, while the side layers would have a reduced barrier height. Such trilayer structure of the tunnel barrier results in accelerated tunneling at higher voltages. This property is what makes the crested barrier junctions a viable candidate for pertinent applications, such as nonvolatile memory cells.
The sample barrier wafers examined were fabricated in situ using a cryopumped vacuum system with a base pressure of 5E-08 Torr. The fabrication process starts with the deposition of a 100 nm niobium base (Nb) electrode using dc magnetron sputtering on a two-inch oxidized silicon wafer (Si02). Following this procedure, the base electrode is blanketed with 100 nm of aluminum film also using dc magnetron sputtering. The oxide is produced by exposure of the aluminum to an oxygen atmosphere for a certain period of time. The least oxidized of the samples, Cr02, was exposed to oxygen at 2.5 Torr for ten minutes, to an exposure of approximately 2E+05 Pa·s, the moderately oxidized sample Cr05 had an exposure of 3E+07 Pa·s after forty minutes in a 100 Torr oxygen environment, and the most oxidized wafer, Cr12 had an exposure of 2E+10 Pa·s after forty hours in a 100 Torr oxygen environment. These ranges are designed to efficiently model every thickness of barrier from very thin barriers near the crossover between resonant and direct tunneling, such as Cr02, to the maximum thickness of unassisted oxide growth (Cr12).
Measurements were performed on several junctions with areas of 3*3µm2 or 30*30µm2 at liquid helium temperatures (4.2K) namely: ten, eleven, and sixteen of Cr02, eight, nine, ten, eleven, and sixteen of Cr05, and junctions seven, eight, eleven, sixteen, twelve, and fifteen (only junctions twelve and fifteen have areas of 30*30µm2) of Cr12. These measurements (current versus voltage curves) were performed using the universal testing setup Octopux. This system uses a series of analog to digital converters to provide dc current biasing, which is measured using the voltage drop across a 2kO loading resistor connected in series with the barrier junction. The measurements were then recorded using a high precision Keithley 2001 multimeter. Data acquisition and visualization were performed with Xlisp, a built-in programming language. Using this data the experimental I-V curves and the more sensitive experimental conductance (G) of the sample versus voltage, which is calculated using the equation: dI/dV (the derivative of the current with respect to voltage) were plotted. Also, the theoretical current versus voltage curve and the theoretical conductance were calculated using the transmission coefficient (the ratio of the electrons that tunnel through the potential barrier to the electrons incident on the barrier) found from the exact solution of the Schrödinger equation by a MATLab computer code.
By comparing these electrical properties of the barrier relationships between them can be made and by comparing these properties to the chemical properties of a chip, the conductance and thus structure of the chip can be optimized. Current results show that there is a direct relationship between average barrier height and thickness. For our samples, the highest barrier height was 1.64 eV. This is to be compared with the 3.5 4eV for sapphire (Al2O3) reported in the literature. However, this disparity of results is not surprising because the Al2O3 grown in this method is known to have an amorphous structure rather than a crystalline structure. Therefore, further optimization and testing of the samples are needed and ongoing.
The development of trilayer crested tunnel barriers may be a forerunner of great improvements in commercial nonvolatile semiconductor memories in which digital bits are stored as a minute electrical charge of a small "floating gate." Equipped with crested barriers, such memory cells would be able to combine a standard ten-year retention time with sub-10 nanosecond write/erase times, which today requires one microsecond, making current technology not applicable to bit-addressable applications. Thus, the crested barrier memory cells may be used in fast bit-addressable nonvolatile random access memories with increased scalability that could decrease its size to the nanometer range, leading to memory devices in the terabit range.
This research was supported by the Air Force Office of Scientific Research and a Simons Fellowship.