Low Voltage Clocking Methodologies for Nanoscale ICs
January 16, 2018
Light Engineering room 250
Advisor: Prof. Emre Salman
Abstract: Power consumption has emerged as a key design objective for almost any application. Low swing/voltage clock distribution was proposed in earlier work as a method to reduce power consumption since clock networks typically consume a significant portion of the overall dynamic power in synchronous integrated circuits (ICs). Existing works on low voltage clocking, however, suffer from multiple issues, making these approaches impractical for industrial circuits. For example, most of the existing studies sacrifice performance when lowering the supply voltage of a clock network, such as clock networks developed for near-threshold computing. The primary objective of this dissertation is to develop a low voltage clocking methodology without degrading circuit performance (operating frequency) or clock network characteristics (skew and slew). This objective is achieved through two primary research tasks: (1) a novel D flip-flop cell that can reliably operate with a low voltage clock signal and a nominal voltage data signal, (2) a slew-driven clock tree synthesis (CTS) methodology to satisfy tight slew constraints at scaled supply voltages, while lowering the overall power consumption of the clock tree. Furthermore, a novel level-up shifter with dual supply voltage is developed for selective low voltage clocking with highly aggressive design constraints. A useful clock skew methodology for gated low voltage clock trees is also proposed to relax the timing constraints of Enable paths. These proposed methodologies were integrated into existing digital design flows and evaluated using several benchmark and large-scale industrial ICs. Specifically, for an industrial 4-core application processor with approximately 1 million gates and implemented in 28 nm FD-SOI CMOS technology, the proposed slew-driven CTS methodology achieves up to 15% reduction in clock tree power while satisfying the skew and slew constraints. Furthermore, for a 64-point FFT core with approximately 120K gates and implemented in 45 nm CMOS technology, the simultaneous use of the proposed DFF cell and slew-driven CTS methodology achieves up to 48% reduction in the overall clocking power under similar performance constraints.